A 12-bit, 200MS/s digitally calibrated pipeline ADC with Embedded Sample and Hold

Abstract

This paper introduces a 12-bit pipeline Analog to Digital Converter (ADC) using 1.2V and 0.13μm CMOS technology. The first stage utilizes the Embedded Sample and Hold technique to eliminate the dedicated power hungry Sample and Hold circuit. Low gain Opamps are used with a Foreground Digital Calibration scheme to account for the Opamp's finite gain and non-linearity. The ADC consumes 65 mW and achieves a maximum SNDR of 68.5 dB with an SFDR up to 80 dB which corresponds to a Figure of Merit (FOM) of about 160 fJ/step.