System-on-Chip Design Methodology for a Statistical Coder

Abstract

In this paper, we propose a system-on-chip software hardware co-design methodology for a statistical coder. We use the context adaptive binary arithmetic coder (CABAC) used in the main profile of the H.264/AVC video coding standard as a design example. The design methodology first involves performance and complexity analyses of the existing CABAC reference software, and thus the top-level CABAC software hardware architecture can be conceptualized. The design is aimed to strike a balance between software modules and hardware modules based on design constraints. Verification is performed by comparing the compressed bit stream generated by the reference CABAC SW (without any HW assisted circuitries), with that output by the top-level CABAC architecture (with HW assisted circuitries). Standard video test sequences have been used for verification purpose. The CABAC architecture is then put within the system-on-chip frame work where system bus and its signals, input/output FIFO buffers, debug structures, reset circuit, etc. are designed into. Compared to existing statistical coders, this design is aimed for significant coding time saving by balancing timing between software modules and hardware modules, is well verified with standard video test sequences, and is reusable as an IP in a SoC environment