Structural and Device Considerations for Vertical Cross Point Memory with Single-stack Memory toward CXL Memory beyond 1x nm 3DXP

Abstract

In this paper, we propose the structure of the 3D vertical cross point memory (3DVXP) having byte-addressability and discuss the possible challenges and requirements from the structural point of view. The necessity of a poly-Si vertical transistor for column selection and the feasibility of current drivability are presented. The structure driven parasitic resistance and capacitance problems on the device performances are discussed, and the resulting trade-off between the operation speed and the cell density is provided. We also demonstrate the advantage and the feasibility of the selectable memory, based on the memory-selector duality, for the application of 3DVXP.