Min-Chul Sun, Sang Wan Kim, Garam Kim, H. Kim, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park
{"title":"Scalable embedded Ge-junction vertical-channel tunneling field-effect transistor for low-voltage operation","authors":"Min-Chul Sun, Sang Wan Kim, Garam Kim, H. Kim, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park","doi":"10.1109/NMDC.2010.5652410","DOIUrl":null,"url":null,"abstract":"While a tunneling field-effect transistor (TFET) is an attractive candidate for sub-20 nm ultra-low-power device, high ION/IOFF and on-current are rarely reported with the deep-submicron structures. In this study, we propose a practical novel TFET structure with vertical channel and Ge junction, which shows high current ratio, low subthreshold swing and relatively high current even when the minimum device dimension is smaller than 20 nm. To find the optimum design, the off-state injection of a short-channel TFET and optimization of the source-side junction are studied by simulation.","PeriodicalId":423557,"journal":{"name":"2010 IEEE Nanotechnology Materials and Devices Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Nanotechnology Materials and Devices Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NMDC.2010.5652410","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18
Abstract
While a tunneling field-effect transistor (TFET) is an attractive candidate for sub-20 nm ultra-low-power device, high ION/IOFF and on-current are rarely reported with the deep-submicron structures. In this study, we propose a practical novel TFET structure with vertical channel and Ge junction, which shows high current ratio, low subthreshold swing and relatively high current even when the minimum device dimension is smaller than 20 nm. To find the optimum design, the off-state injection of a short-channel TFET and optimization of the source-side junction are studied by simulation.