Hardened By Design All-Digital Pulsed Multiplying DLL for DDR2-3 Interfaces

Abstract

This abstract proposes a novel radiation hardened all-digital multiplying delay locked loop. The design uses pulse-clocking to create a high frequency clock for use in DDR2 and DDR3 data recovery and transmit without intermediate frequency generation. Implementation on a 55 nm low standby power process, can achieve DDR3-800 speeds at all corners with a peak to peak jitter of 22 ps. The energy dissipation is 14 pJ/MHz in active mode and 1.65 pJ/MHz in low-power standby mode. The full block area is 0.11 mm2. Control and filter circuits use a proven interleaved automated placement and routing providing full triple mode redundant domain separation for multiple critical node collection immunity.