An IDDQ BIST approach to characterize phase-locked loop parameters

Abstract

In this work, a new IDDQ built-in self-test (BIST) solution is proposed to provide accurate on-chip current measurements for phase-locked loops (PLLs) found in deep-submicron system-on-chip (SoC) products. The proposed method characterizes PLL loop parameters to increase test quality with minimum additional test time and 4.5% accuracy in IBM 65 nm technology. A self-correction mechanism accompanies the proposed BIST to recover performance variations resulting from excessive process variation found in high-volume manufacturing (HVM). The proposed IDDQ BIST circuit's performance is evaluated in silicon using 0.18μm technology and achieves 2% accuracy with only 1.7% additional PLL area overhead. Extensions to other analog mixed signal circuit blocks should be possible.