Pulse width multiplier circuit with application to digital phase measurements

M. A. El-Ela, A. Telba
{"title":"Pulse width multiplier circuit with application to digital phase measurements","authors":"M. A. El-Ela, A. Telba","doi":"10.1109/NRSC.1999.760885","DOIUrl":null,"url":null,"abstract":"A digital, frequency independent, phase meter is discussed. Wide frequency range of operation is obtained by using a digital pulse width multiplier to multiply the pulse width of the phase comparator output, (S-R flip flop for example). The clock pulses to be counted will be then the reference input signal instead of conventional crystal controlled oscillator clock sources-the elimination of the PLL used to multiply the clock frequency makes it possible to operate without the limit of the PLL lock-in range. Another advantage is simplicity and elimination of gating error.","PeriodicalId":250544,"journal":{"name":"Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NRSC.1999.760885","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

A digital, frequency independent, phase meter is discussed. Wide frequency range of operation is obtained by using a digital pulse width multiplier to multiply the pulse width of the phase comparator output, (S-R flip flop for example). The clock pulses to be counted will be then the reference input signal instead of conventional crystal controlled oscillator clock sources-the elimination of the PLL used to multiply the clock frequency makes it possible to operate without the limit of the PLL lock-in range. Another advantage is simplicity and elimination of gating error.
应用于数字相位测量的脉宽倍增电路
讨论了一种数字式、频率无关的相位计。宽频率范围的操作是通过使用一个数字脉宽倍增器乘以相位比较器输出的脉宽,(S-R触发器为例)。要计数的时钟脉冲将是参考输入信号,而不是传统的晶体控制振荡器时钟源-消除用于乘以时钟频率的锁相环使得可以在没有锁相环锁定范围限制的情况下工作。另一个优点是简单和消除门控误差。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信