Hardware SAT Solver-based Area-efficient Accelerator for Autonomous Driving

Abstract

Today's embedded systems applications consisting of a variety of tasks are becoming larger and more complex. Hence, when multiple tasks need to be accelerated, designing a dedicated accelerator for each task would be difficult on small devices due to large area overhead. In this study, we propose an efficient accelerator for autonomous driving, which is a theme of a design competition held at International Conference on Field Programmable Technology. Focusing on two key tasks (path planning and object detection), we formulate each of them as a satisfiability problem (SAT) and use a hardware SAT solver as a common accelerator for these tasks. We present efficient problem formulation methods for solving these tasks on a small FPGA. Experimental results show the effectiveness of our work for these tasks.