Three dimensional modeling of SOI four gate transistors

Abstract

A mathematical model is developed to determine the 3-D potential distribution of a fully-depleted silicon-on-insulator (SOI) four-gate transistor (G4-FET). The potential distributions along the channel and between the junction-gates are assumed to be parabolic due to short channel effect. Using these two assumptions, the 3-D potential distribution model is developed. From the 3-D model, expression for threshold voltage is derived considering all possible charge conditions at the back surface. The proposed models successfully correlate the effect of all four gates and consider the impact of channel length, drain voltage and other device dimensions.