Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors

Abstract

As will be shown, the architecture and gate stack processing have a clear impact on the low-frequency noise performance of horizontal nanowire (NW) transistors. In this work, the noise of single nanowires is compared with stacked devices. For single NWs, junctionless (JL) transistors tend to exhibit a better noise performance than inversion mode (IM) counterparts. In addition, a clear impact of the type of metal gate (MG) on the 1/f noise Power Spectral Density (PSD) will be demonstrated.