A fast, asP*, RGD arbiter

Abstract

This paper presents the design of a high-throughput, low-latency, asP*, RGD arbiter. Spice simulations for an implementation in a 0.8 /spl mu/ CMOS process show a request-to-grant delay of 0.74 ns and a done-to-grant-delay of 0.42 ns. Maximum throughput of requests from a single client is one grant per 1.8 ns; if both clients make request aggressively, the arbiter can produce one grant per 1.2 ns. In addition to presenting a high-performance design, this paper examines trade-offs in performance driven design. In particular, logic delay seems to dominate metastability concerns when optimizing performance.