Verification of the FTSC microprogram

Abstract

At ISI, we are halfway into a two year research program in microcode verification. We are focussing our attention on microcode that implements a target instruction set. The Fault-Tolerant Spaceborne Computer is a typical microcoded machine and we are using an early version of it as the prime example for the present work. example for the present work. The host machine decodes a 78 bit microinstruction into 37 separate fields. About 750 microinstructions are used to implement the target instruction set. The target machine is word oriented with 32 bit words. The CPU has eight general purpose registers and carries out the usual repertoire of integer, logical and floating point operations.