Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core

Abstract

In this paper, we propose efficient scalable nonvolatile flip-flops (NV-FF) with single-stage pulsed latch which is explored as the flip-flop core in hybrid CMOS/MTJ (magnetic tunnel junction) integration. Typical full-custom FF cores are implemented with a 28nm ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. The performance analysis takes into account sensing delay, dynamic power, leakage power and process variations. Results show that the transmission gate pulsed latch (TGPL) based NVFF exhibits enhanced performance compared to conventional master-slave structure, with improved variability, 15.7% fast timing metric, 76% dynamic, 79% leakage power reduction and 30% layout area reduction in multi-bit NV-FF hybrid circuit integration. The pulsed latch FF core can enhance NVFF scalability with increased energy-delay and layout efficiency, as well as reduced active and leakage energy.