Imapct of SiN on Performance in Novel CMOS Architecture Using Substrate Strained-SiGe and Mechanical Strained-Si Technology

Abstract

In this work, we report the demonstration of a novel CMOS process with substrate-strained-SiGe pMOSFET and mechanical-strained Si nMOSFET fabricated on one chip. The device structure combines the advantages of compressively SiGe materials and tensile Si induced by SiN layer to achieve higher carrier mobility. Moreover, due to the separation process of two kind devices, individual MOSFETs was tuned independently to their optimum performance on the same wafer and show a great flexibility for developing next-generation high-performance CMOS