Power estimation of a LUT-based MPGA

Abstract

Power consumption is a limiting factor to FPGA viablility in applications such as portable devices. LUT-based mask-programmable gate-arrays (LUT-based MPGAs) are alternatives to reach the fast turnaround times of an FPGA with low design cost and low power consumption. A LUT-based MPGA preserves the same logic-structure of a LUT-based FPGA. Unlike FPGAs, the programmable configuration and interconnect is mask-programmable. This paper describes a methodology to estimate power consumption in a LUT-based MPGA. The proposed methodology uses a gate-power estimation tool. The dynamic and static powers of the basic-gates are modeled in a library. The interconnect is easily modeled because the programmable metal-masks are predefined. A comparison with a transistor-level simulation shows an average difference of 20% with the final power result. The experiments show that the major contributor of the power consumption in the MPGA is the clock network. Power results on MPGAs and FPGAs are compared. The dynamic power consumption in the logic is reduced by 73%. The major power reduction is observed in the interconnects. Static power consumption in the LUT-based MPGA is insignificant compared its dynamic power consumption