Constraint abstraction for vectorless power grid verification

Abstract

Vectorless power grid verification is a formal approach to analyze power supply noises across the chip without detailed current waveforms. It is typically formulated and solved as linear programs, which demand intensive computational power, especially for large-scale power grids. In this paper, we propose a constraint abstraction technique to reduce the computation cost of vectorless verification. The boundary condition of a subgrid is modeled by boundary constraints, which enable efficient calculation of conservative bounds of power supply noises in a divide-and-conquer manner. Experimental results show that the proposed approach achieves significant speedup over prior art while maintaining good solution quality.