Understanding the impact of High-k Post Deposition Anneal Temperature on FinFET Reliability – Trade-offs, optimization and mitigation

Abstract

The impact of high-k (HK) PDA anneal temperature (T) on FinFET reliability is studied comprehensively. Reducing the anneal temperature improves performance, but degrades BTI, HCI and TDDB. For BTI, the prefactor increases and voltage acceleration reduces for lower temperature, while time slopes remain unchanged. Reducing anneal temperature increases charge trapping behavior. For TDDB, voltage acceleration shows weak modulation to anneal temperature. HCI degrades due to lower anneal temperature for PFET. The underlying physical mechanism is correlated to IL thickness and HK crystallinity. Mitigation by post gate stack thermal budget optimization is presented.