Impact of interconnect technology scaling on SOC design methodologies

Abstract

The impact of interconnect technology scaling on RC delay is a well-researched topic. This paper provides a fresh perspective on the impact of interconnect technology scaling on SOC designs. The impact of intra-cell RC parameters on circuit performance is described. The importance of managing the intra-cell RC scaling for low power designs is emphasized. The impact of fill metal and CMP on analog circuits is illustrated. The significance of accurate RC extraction for validating the performance and signal integrity of SOC designs is discussed. Using a 64M transistor SOC design, the effects of noise and EM reliability are highlighted. The impact of inductance on clock skew, noise and reliability are discussed.