Area/performance evaluation of digit-digit GF(2K) multipliers on FPGAS

Abstract

This work describes novel hardware architectures for GF(2k) multipliers using a digit-digit approach. Contrary to the bit-serial and digit-serial approaches previously addressed in the literature, we consider the partition of the multiplier, multiplicand and modulus in several digits and execute a field multiplication in an iterative way, like in a software implementation but exploiting the parallelism in the operations. We focused on parametric designs that allow to study area-performance trade offs when the multipliers are implemented in FPGAs. This study would guide a designer to select the most appropriate configuration based on the digits sizes in order to meet system requirements such as available resources, throughput, and efficiency. Although the proposed multiplier can be implemented for any finite field of order k, we provide implementation results for GF(2163) and GF(2233), two recommended finite fields for elliptic curve cryptography. For specific digit sizes, our proposed digit-digit multiplier uses considerably less area than a bit-serial multiplier with a penalization in the timing. Compared to a digit-serial implementation, area resources can be saved with still an improvement in the timing respect to a bit-serial implementation.