Area/performance evaluation of digit-digit GF(2K) multipliers on FPGAS

M. Morales-Sandoval, A. Díaz-Pérez
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引用次数: 4

Abstract

This work describes novel hardware architectures for GF(2k) multipliers using a digit-digit approach. Contrary to the bit-serial and digit-serial approaches previously addressed in the literature, we consider the partition of the multiplier, multiplicand and modulus in several digits and execute a field multiplication in an iterative way, like in a software implementation but exploiting the parallelism in the operations. We focused on parametric designs that allow to study area-performance trade offs when the multipliers are implemented in FPGAs. This study would guide a designer to select the most appropriate configuration based on the digits sizes in order to meet system requirements such as available resources, throughput, and efficiency. Although the proposed multiplier can be implemented for any finite field of order k, we provide implementation results for GF(2163) and GF(2233), two recommended finite fields for elliptic curve cryptography. For specific digit sizes, our proposed digit-digit multiplier uses considerably less area than a bit-serial multiplier with a penalization in the timing. Compared to a digit-serial implementation, area resources can be saved with still an improvement in the timing respect to a bit-serial implementation.
fpga上数位GF(2K)乘法器的面积/性能评估
这项工作描述了使用数字-数字方法的GF(2k)乘法器的新硬件架构。与之前在文献中提到的位串行和数字串行方法相反,我们考虑了乘数、乘数和数模的划分,并以迭代的方式执行字段乘法,就像在软件实现中一样,但利用了操作中的并行性。我们专注于参数化设计,允许研究在fpga中实现乘法器时的面积性能权衡。该研究将指导设计人员根据数字大小选择最合适的配置,以满足可用资源、吞吐量和效率等系统需求。虽然所提出的乘法器可以在任何k阶的有限域上实现,但我们提供了GF(2163)和GF(2233)这两个推荐的椭圆曲线加密有限域的实现结果。对于特定的数字大小,我们提出的数字-数字乘法器比位-串行乘法器使用的面积要小得多,并且在时序上有惩罚。与数字串行实现相比,可以节省区域资源,但与位串行实现相比,在时序方面仍有改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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