{"title":"Efficient implementation of DVR's control","authors":"P. García-Vite, J. Ramirez, J. Rosas-Caro","doi":"10.1109/PES.2009.5275931","DOIUrl":null,"url":null,"abstract":"This paper reports the detailed implementation of a three-phase dynamic voltage restorer (DVR). Such devices have gained popularity among the PWM-based compensation series devices. Two cases are studied: balanced and unbalanced voltage sags, which are the most frequent disturbances. For the latter case, a modified delta rule is used to transform the three-phase voltage into positive, negative, and zero sequences. The model of the LC filter is explained and a Software Phase Locked Loop (SPLL) based on Trans-vector-type is developed. DVR's simulations are provided. Hardware implementation employs a fixed point Digital Signal Processor and power electronics devices, as well as an SPLL. Experimental results on voltage sags have been dealt with to corroborate the adequate DVR performance.","PeriodicalId":258632,"journal":{"name":"2009 IEEE Power & Energy Society General Meeting","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Power & Energy Society General Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PES.2009.5275931","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper reports the detailed implementation of a three-phase dynamic voltage restorer (DVR). Such devices have gained popularity among the PWM-based compensation series devices. Two cases are studied: balanced and unbalanced voltage sags, which are the most frequent disturbances. For the latter case, a modified delta rule is used to transform the three-phase voltage into positive, negative, and zero sequences. The model of the LC filter is explained and a Software Phase Locked Loop (SPLL) based on Trans-vector-type is developed. DVR's simulations are provided. Hardware implementation employs a fixed point Digital Signal Processor and power electronics devices, as well as an SPLL. Experimental results on voltage sags have been dealt with to corroborate the adequate DVR performance.