Ferroelectric-CMOS Nonvolatile Memory Development

Abstract

Introduction: A Ferroelectric-CMOS nonvolatile memory technology is being developed at Sandia National Laboratories. Process integration, design and performance issues are being addressed and the technology is being evaluated for applicability to Sandia missions and commercialization. Two basic versions of a 256 bit prototype memory have been designed and fabricated using sol-gel PZT. Tests have yielded fully functional ferroelectric, FE, nonvolatile memories. Program and Design: The program focuses on the development of a 256 bit memory with conservative design rules in order to emphasize ferroelectric performance and process integration issues while not being dominated by circuit density issues and small layout tolerances. The typical feature size is 4 microns and the FE capacitor is 5x5 microns. The two design versions are a dynamic RAM type memory and a shadow RAM array. The memory cell in the DRAM array consists of 4 transistors (2 complementary pair access gates) and two ferroelectric capacitors (bit and not-bit) as shown in Fig. 1. A differential latch sense amplifier is used to detect lhe voltage difference between bit