Comparative of performance and delays between topologies cells 2T1C, 3T1C, and 4T2C for DRAM

Abstract

The basic memory cell is a fundamental circuit in various applications of modern electronics. Today, dynamic random access memory (DRAM) is one of the most relevant digital building blocks largely deployed as on-board cache memory in processors. In this work, at the design level in 180 nm technology, the different topologies for a DRAM cell are developed as 2T1C, 3T1C, and 4T2C. Evaluating its energy performance and delays during the writing and reading stages, through the figure of merit, the design and simulation of the DRAM topologies were carried out in the Tanner L-Edit IC CAD software platform.