Regression Analysis of Static Noise Margin and Transconductance for Underlap Lengths of FinFET

Abstract

In the sub-nanometer regime, the polysilicon gate has been a better replacement by the metal gates. However, metal gates are prone to variation due to their granular nature. The present research work analyzes the effect of Titanium Nitride (TiN) metal gate for various underlap FinFET devices. Numerical values for Static Noise Margin (SNM) and Transconductance (${g}_{m}$) have been realized for three different underlap lengths (3 nm, 6 nm, and 9 nm) FinFET device. The result shows that underlap length plays a vital role in the sub-nanometer FinFET device. Furthermore, a static noise margin analysis has been performed for the SRAM cell. This work suggests that the large underlap FinFET devices are robust from variations introduced by TiN metal fluctuations.