Stochastic inductance model of on chip active inductor

Abstract

In this study, the model which describes the effect of the stochastic nature of the bias current to the inductance of the on chip active inductor has been proposed. This study has been performed based on the up to dated CMOS technology. For the model derivation and verification, the fundamental concept of stochastic process and goodness of fit test have been adopted respectively. The model can accurately capture the stochastic behavior of the resulting inductance with sufficient confidence i.e. 95% with the K-S test. The proposed model is applicable to any CMOS on chip active inductor. Hence, it has been found to be a convenience tool for the design of various active inductor based communication circuits and systems as its aim.