3-layered capacitive structure design for MEMS inertial sensing

Abstract

In this paper a two-terminal capacitive structure is presented in which a novel architecture with a double interleaved (interdigitated) scheme is introduced. This structure was originally conceived as a mechanism to achieve a greater capacitance between the plates (terminals) of an integrated capacitor using a relatively smaller design area in the standard 0.5μm, two polysilicon and three metal layers (2P3M) CMOS technology. This work presents the design and theoretical analysis of a three-metal interleaved structure used as a varactor tied down to the proof mass of an integrated CMOS-MEMS accelerometer where the active devices are floating-gate transistors (FGMOS) with a variable capacitive coupling coefficient. Nevertheless, the three-layered geometrical scheme may have a wide range of applications across the MEMS technology.