Optimal body bias selection for leakage improvement and process compensation over different technology generations

Abstract

We present techniques to determine the optimal body bias (forward or reverse) to minimize leakage current and compensate process variations in scaled CMOS technologies. A circuit trades off sub-threshold leakage with band-to-band tunneling leakage at the source/drain junctions to determine the optimal substrate bias for different technology generations and under process variations. Using optimal body bias results in 43% and 42% savings in leakage for predictive 70 nm and 50 nm NMOS devices, respectively. This technique also reduces the effects of die-to-die and intra-die process variations in transistor length and supply voltage by 43% and 60%, respectively, in 50 nm NMOS devices, resulting in improved yield.