A Sequential Test Generator with Explicit Elimination of Easy-To-Test Faults

Abstract

This paper combines the advantages of forward and reverse time approaches to generate the test vectors for a sequential circuit. The algorithm uses PODEM and nine-value logic model. Two new classes of faults called 0-step and 1-step testable faults are defined. The tests for these faults are generated based on known states. These faults are regarded as easy-to-test because the justification and propagation sequences are already known. The percentages of such faults are experimented for MCNC benchmark circuits. Fault simulation of the vectors for such faults is fast because fault simulation of justification sequences is not needed. Fewer test vectors is needed when a fault is identified as 0-step and 1-step testable because the justification sequence of the fault can be shared with other faults. The tests €or the faults other than 0-step and 1-step testable faults are obtained using partial state enumeration, fault free justification and propagation method. The program is written on top of STEED which is a UC Berkley sequential test generator. The CPU time improvement can be up to 150% faster SEED and the number of test vectors can be 38% less than the set generated by STEED.