A 1.65-V 176-μW 104-dB Continuous Time Delta-Sigma Modulator for Sensor Applications

Abstract

This paper presents a low-noise single-loop third-order single-bit continuous-time (CT) Delta-Sigma modulator for sensor applications. The modulator employs the CIFF-B structure and chopping technique to reduce the power consumption and low-frequency noise. The FIR feedback DAC is adopted to reduce the sensitivity of CT ΔΣ modulators to clock jitter, and the method of moments is used to design the coefficients of loop filter. The chopping frequency is also designed carefully to avoid the noise aliasing effect, and modulator coefficients and circuit implementation have been optimized for low power. The modulator, implemented in a 150nm CMOS technology with a core area of 0.48mm 2, achieves a 107dB peak SNR and a 104dB peak SNDR over a 1kHz signal bandwidth. The power consumption is 176µW at 1.65V supply voltage.