Design Defect Diagnosis in a Buggy Model of SPARC T1 Processor Using Random Test Program Generator

Abstract

Verification has indisputably become the primary challenge today with recent industry studies estimating that half of all chips manufactured require one or more re-spins. Ideally the performance of the design should be verified for all possible circumstances under which it might be operated in the real world. Unfortunately, it requires a long time to generate and run test sequences. Under the time to market pressure, it is very time consuming to write all test programs manually. This brings about the necessity of developing a random test program generator (RTPG). Proposed RTPG is for verifying the SPARC processor architecture. The approach is in classifying general type of bugs that can get into the EXU unit of SPARC T1 processor design and introducing design defects in the RTL. Several defective models are developed covering the entire functional blocks in the EXU and several coverage models for the test cases run on the defective design were also developed. The direct and random test case generation is applied on the buggy model and various coverage reports are analyzed. This work tends to look back at the fact that verification is a process that is never truly complete. We understand that designs are error-prone and so, the objective of verification is to detect the errors. Yet, no one can really prove that the design is error-free.