Modeling of through-silicon via's (TSV) with a 3D planar integral equation solver

Abstract

Through-silicon via (TSV) interconnection technology is seen as a key enabling technology for stacking silicon dies and building 3D chips. In this paper, we present a novel technique to enable the modeling of through-silicon via interconnects within a 3D planar integral equation solver. The technique is capable of modeling both the dielectric isolation effects of the TSV oxide and the metal-oxide-semiconductor (MOS) depletion effects at the TSV oxide - silicon bulk contact regions.