SEU effects on static and clocked cascade voltage switch logic (CVSL) circuits

Abstract

In order to design radiation-hardened LSIs for space applications, single event transient upset effects on cascade voltage switch logic (CVSL) circuits have been investigated using SPICE. Static and clocked CVSL test circuits have been successfully fabricated utilizing a double polysilicon double metal N-well CMOS technology. The both CVSL circuits have been confirmed to function correctly by the fabricated chip measurements. SET simulation results have confirmed that the CVSL circuits have high SET immunity. SET immunity for the CVSL circuits is compared to that for the conventional CMOS circuits, showing that the CVSL is a candidate for a SET immune spaceborne logic circuit. Furthermore, the static CVSL and clocked CVSL are compared.