A direct conversion WLAN receiver

Abstract

A direct conversion receiver for WLAN 802.11b is presented in 0.18/spl mu/m CMOS technology. It contains a complete receiver chain with low noise amplifier, I/Q mixer, programmable gain amplifier and base band filter. A 4.8GHz divider is used to generate 2.4GHz quadrature clock for I/Q mixer. The reception path is dc coupled and a feed back low pass filter is added to reduce the dc-offset and 1/f noise. The noise figure of receiver is 5.2dB, the IIP3 is -14.5dBm at high gain setting. With the supply voltage of 1.8V, the over all power consummation is about 100mW. The chip area with pads is 2.6mm/spl times/2.5mm.