Hardwired BIST architecture of SRAM

Abstract

This work proposed an on-chip architectural design, validation and feasibility of a BIST for 8×8 SRAM using 0.18 μm UMC technology in Cadence Virtuoso and Spectre Tool for storage and retrieval faults detection. As, the technology shrinks and share of memories in complex systems increases, memories become susceptible to faults. Storage and retrieval faults are genuinely faced by SRAM. This type of fault occurs due to improper storage or retrieval of data i.e. breakage in the word line or in bit line. Thus, it become a major issue for test engineers, as area overhead is a constraint. From the results obtained, it has been observed that the proposed architecture, for detecting the storage and retrieval faults is working properly but the area and power due to BIST is increased with comparison to the circuit under test alone. The feasibility of proposed BIST architecture is checked by calculating the area and power overhead of BIST for large size memories.