Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor

A. Lambrechts, P. Raghavan, M. Jayapala, F. Catthoor, D. Verkest
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引用次数: 19

Abstract

Modern portable embedded devices provide continuously more features and need processors that are of increasingly higher performance in order to sustain very demanding multimedia and wireless applications. Larger amounts of flexibility need to be built in and the same processor needs to be used for a wide range of evolving products, while very strict energy constraints need to be met in order to provide a long battery life. Coarse Grained Reconflgurable Architectures (CGRAs) provide a mix of flexible computational resources and large amounts of programmable interconnect. However, this programmable interconnect is on average consuming about 50% of the core's energy consumpion for state of the art interconnection topologies. In this work we present an optimized interconnection implementation that selectively activates only the connections that are being used in a certain cycle, in order to reduce the energy spent in the interconnect. Using this optimization, we show the effect on the energy and performance trade-off for the ADRES CGRA. The energy cost of the optimized interconnect topologies that provide a higher performance can be reduced significantly, reducing the total energy consumption of the core with up to 40%. This will enable designers to develop more efficient architectures, tuned to a targeted application domain.
基于能量感知的粗粒度可重构处理器互连优化
现代便携式嵌入式设备提供了越来越多的功能,并且需要性能越来越高的处理器来支持非常苛刻的多媒体和无线应用。需要内置更大的灵活性,并且需要将相同的处理器用于各种不断发展的产品,同时需要满足非常严格的能量限制,以提供更长的电池寿命。粗粒度可重构架构(CGRAs)提供了灵活的计算资源和大量可编程互连的组合。然而,对于最先进的互连拓扑,这种可编程互连平均消耗约50%的核心能耗。在这项工作中,我们提出了一种优化的互连实现,该互连实现选择性地仅激活在特定周期中使用的连接,以减少互连中消耗的能量。使用此优化,我们展示了对ADRES CGRA的能量和性能权衡的影响。优化后的互连拓扑可以显著降低能耗,提供更高的性能,降低核心总能耗高达40%。这将使设计人员能够开发更有效的体系结构,并针对目标应用领域进行调整。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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