A 60-GHz SPST switch in 65-nm CMOS technology

Abstract

An enhanced circuit model is developed for a 60-GHz single-pole single-throw (SPST) switch in 65nm CMOS technology in this paper. The enhanced circuit model involves the modeling of the drain-to-source parasitic capacitances that are introduced by the overlapped multi-finger drain-to-source metallization of the transistors and also the modeling the distributive and coupling effect of lines interconnection, testing pads and ground metals. The enhanced circuit model leads to an improved agreement between the simulated and measured performance over the frequency range from 1 to 170 GHz.