An automated design methodology for EEPROM cell (ADE)

J. Portal, L. Forli, H. Aziza, D. Née
{"title":"An automated design methodology for EEPROM cell (ADE)","authors":"J. Portal, L. Forli, H. Aziza, D. Née","doi":"10.1109/MTDT.2002.1029774","DOIUrl":null,"url":null,"abstract":"The objective of this paper is to present an Automated Design methodology for EEPROM cell (ADE). This method focuses on EEPROM cell geometry automatic generation for a targeted program window including constraints like robustness to process variation, program high voltage and electric field minimization. The method is based on a mathematical model generated with a \"Design Of Simulation\" (DOS) technique. The DOS technique takes as input, simulations results of a floating gale transistor for different given geometries and program high voltages. It produces, as output, polynomial equations of the threshold voltages and maximal electric field injunction of the geometric parameters and of the program high voltage. Using those equations, the design process is realized in two steps. In a first step, a set of cells (geometry and high voltage) meeting a targeted threshold voltages window is generated. From this set of cells, the optimal cell is selected under robustness, high voltage and electric field minimization criteria.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2002.1029774","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

The objective of this paper is to present an Automated Design methodology for EEPROM cell (ADE). This method focuses on EEPROM cell geometry automatic generation for a targeted program window including constraints like robustness to process variation, program high voltage and electric field minimization. The method is based on a mathematical model generated with a "Design Of Simulation" (DOS) technique. The DOS technique takes as input, simulations results of a floating gale transistor for different given geometries and program high voltages. It produces, as output, polynomial equations of the threshold voltages and maximal electric field injunction of the geometric parameters and of the program high voltage. Using those equations, the design process is realized in two steps. In a first step, a set of cells (geometry and high voltage) meeting a targeted threshold voltages window is generated. From this set of cells, the optimal cell is selected under robustness, high voltage and electric field minimization criteria.
EEPROM单元(ADE)的自动化设计方法
本文的目的是提出EEPROM单元(ADE)的自动化设计方法。该方法侧重于针对目标程序窗口的EEPROM单元几何自动生成,包括对工艺变化的鲁棒性、程序高压和电场最小化等约束。该方法基于用“仿真设计”(DOS)技术生成的数学模型。DOS技术以不同给定几何形状和程序高电压的浮动栅极晶体管模拟结果为输入。它输出几何参数和程序高压的阈值电压和最大电场的多项式方程。利用这些方程,设计过程分两步实现。在第一步中,生成一组满足目标阈值电压窗口的单元(几何和高压)。根据鲁棒性、高电压和电场最小准则,从这组单元中选择最优单元。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信