Design and simulation of a 3rd-order Discrete-Time Time-Interleaved delta-sigma modulator with shared integrators between two paths

Abstract

this paper presents the design and simulation of a 3^rd-order two-path Discrete-Time Time-Interleaved (DTTI) ΔΣ modulator. By exploiting the concept of the time-interleaving techniques and time domain equations, a conventional 3^rd-order Discrete-Time (DT) ΔΣ modulator is converted to a corresponding 3^rd-order two-path DTTI counterpart. For the sake of saving power and silicon area, the integrators between the two paths of the DTTI ΔΣ modulator are shared. Using one set of integrators makes the DTTI ΔΣ modulator robust to path mismatch effects compared to the typical DTTI ΔΣ modulator which has individual integrators in all paths. A problem arises out of sharing integrators between paths which we call the delayless feedback problem. A solution for this problem is proposed in this paper and for an OverSampling Ratio (OSR) of 16 and a clock frequency of 320MHz, a maximum SNR of 76.5dB is obtained.