An input pole tuned switching equalization scheme for high-speed serial links

Abstract

A novel receiver equalization scheme for high-speed links is described in this paper. By per-bit switching the channel-receiver connection, the channel induced inter-symbol interference (ISI) is compensated by receiver (RX) input pole induced ISI. The polarity of the recovered binary bit is adjusted in digital domain to match the transmitted data. An input pole based two-way interleaved switching equalization circuit is proposed and simulated. In comparison with the conventional FIR filter, it improves the output eye width by 63%. This paper provides a new way of converting a low-pass system into a peaking system for link designs, suitable for a broader range of applications.