An 85-GHz Low-Power Low-Noise Amplifier with 15 GHz Bandwidth in 22nm FD-SOI CMOS for 5G Communications

Abstract

In this paper, we introdue a very low-power low-noise millimeter wave amplifier (LNA) with noise-cancellation and noise-reduction techniques. The proposed LNA architecture uses a common-gate input branch to provide wideband input matching. It is followed by one stage of the common-source structure which cancels the noise and distortion of the first stage. The proposed noise-reduction technique is applied to reduce the thermal noise of nMOS transistor in the second stage which reuses the current of the input stage. The input and output matching networks are used to provide 50Ω matching of the input/output ports. We perform a circuit-level analysis that is verified by simulations. The proposed LNA is designed in 22-nm FD-SOI CMOS technology. It achieves a minimum noise Figure (NF) of 4.5 dB over 77–90 GHz bandwidth while consuming only 3.2mW from a 0.8V supply and driving the external 50-Ω load. The -3 dB power gain (S21) is 8.4 dB and IIP3 and IIP2 are -10.5dBm and +25.9 dBm, respectively.