An integrated memory self test and EDA solution

Abstract

Memory built-in self-test (BIST) is a critical portion of the chip design and electronic design automation (EDA) flow. A BIST tool needs to understand the memory at the topological and layout levels in order to test for the correct fault models. The BIST also needs to be fully integrated into the overall EDA flow in order to have the least impact on chip area and have the greatest ease of use to the chip designer.