METHODOLOGY FOR PREDICTING MANUFACTURING YIELD FOR PRINTED CIRCUIT BOARD ASSEMBLY LINES

Abstract

Engineers have few tools to reliably estimate their production capabilities as they introduce new board designs onto their current production lines. This paper presents a methodology to predict the manufacturing yield of a printed circuit board manufactured on a given assembly line. Current techniques for yield estimation are based on process modeling techniques and board design techniques, and the methodology presented in this paper integrates these two approaches. The combined yield methodology consists of a Poisson-based yield model that uses fault probabilities to estimate the yield and an optimization problem that generates the fault probabilities. The optimization problem determines the fault probabilities that minimize the difference between actual yield values and predicted yield values (using the past yield history and design information from various board designs). The resulting fault probabilities represent both component and process faults and are used in the Poisson-based yield model to estimate the yield. The methodology compared favorably with previous models published in the literature. In addition, the methodology is applied to two actual PCB assembly lines and predicts actual yield within 3% for the boards considered.