Integrated DC link capacitor/bus structures to minimize external ESL contribution to voltage overshoot

Abstract

Voltage overshoot is defined by stray series inductance and turn-off time, which must be managed to avoid failure of IGBT's in inverter applications. The total equivalent series inductance (ESL) is dictated by internal switch branch inductance with a significant contribution in the current path to the DC link capacitor. Using traditional topologies, external ESL dominates and by-pass capacitors (“snubbers”) are used to mitigate overshoot. Integrated capacitor/bus designs provide an external ESL comparable to internal values for commercial IGBT's. The minimized ESL regime allows reduced switch turn-off time with slightly increased losses to manage overshoot without the cost, space, weight, dissipation, and reliability associated with by-pass capacitors.