Strength characterization of TEOS and FTEOS interlayer dielectric materials to compare fracture risk in die stack by 3D FE simulation approach

Abstract

Interlayer dielectric (ILD) fracture was investigated to better understand and mitigate failures in the interconnect systems of wafer back-end-of-line (BEOL) stacks. Variation in strength can cause fracture or delamination flaws resulting in reliability issues in the final product due to chip-package interactions (CPI). This study developed means to identify potential strength weaknesses induced during wafer processing. The ILD material has significant impact of introducing weaknesses during wafer production. In this study, two very common ILD materials, tetraethyl orthosilicate (TEOS) and fluorinated tetraethyl orthosilicate (FTEOS) were compared with respect to their fracture toughness in a wafer stack. A combination of mechanical testing, mechanical modeling and simulation were performed to identify fracture parameter of the particular bulk materials and material interfaces, translate them into fracture stresses and compare different BEOL structures with respect to their potential fracture risk. To estimate the critical fracture stress, a simple 2D Finite Element Analysis (FEA) was conducted. In a second step a much more complex 3D sub-modelling approach was used to investigate the specific differences of die locations with respect to fracture risk and considered the BEOL stack metal layout in greater detail. The simulations used stress-based as well as energy-based parameters for comparison. The simulation results showed the correct trend in failure risk as observed in failure analysis.