Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling

Abstract

The continuous semiconductor technology scaling has made on-chip interconnect the major determinant of VLSI design cost and complexity. This necessitates the usage of signaling techniques that reduce the number of long on- chip wires and repeaters. In this paper, we present a point-to-point inter-block on-chip link design that allows simultaneous bidirectional signaling, thus reducing the number of signal lines and repeaters, while achieving high performance. By using accelerating repeaters and inserting a bidirectional latch at the midpoint of the link high performance simultaneous bidirectional signaling can be achieved with significant reduction in repeater and wire counts. We analyze the switching behavior of the proposed on-chip simultaneous bidirectional link (SBL) and find that it suffers from large switching activity overhead. Therefore, an opposite-polarity transition encoding is also proposed to reduce the power overhead of SBL without affecting its performance.