Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devices

Abstract

The effect of the gate to drain capacitance on low voltage operated CMOS devices is investigated. It is found that the Miller and feed-forward effects are enhanced with the reduction of the supply voltage. The reduction of the gate overlap capacitance as well as the threshold voltage and junction capacitance is a key issue to achieve high speed circuit operation at low supply voltage. We propose a low power, high speed T-gate CMOS device with dual gate structure using an amorphous-Si/poly-Si layer. A new process scheme is proposed to prevent boron penetration and to fabricate the T-gate structure effectively. It is found that the new T-gate CMOS with dual gate structure reduces the gate to drain overlap capacitance maintaining high current drivability at low power-supply voltage.