Quantitative analysis for noise generated from share circuitries within DDR3 DRAM

Abstract

Correctable errors, almost single bit errors, can be induced from random data transition in DRAM. In the system, most of CEs are corrected by error correction code, but there is intermittent system down. Several literatures have reported that noise generated from share circuitries is regarded as a cause of soft failure. Noisy environments are one of the unavoidable factors in the high speed, high density, and low power DRAM. For the purpose of finding out noise source, we investigated states of share circuitries with random data transition. BLSA, power transistor, power line, and common plate were also researched with DDR3 DRAMs. A simple model was proposed with the quantitative analysis. Results show that the soft failure occurs when unexpected combination of noise factors happen at once, because the revealed erratic bits have similar characteristics of normal bits, except for the influence on noise.