{"title":"Parallel mapping implementation of AES for Coarse-Grained Reconfigurable Block Encryption Array","authors":"Yuhang Yang, Wei Li, Jinfu Xu, H. Ni","doi":"10.1109/ICASID.2016.7873919","DOIUrl":null,"url":null,"abstract":"In this paper, we explore different parallel mapping implementations of Advanced Encryption Standard (AES) on the Coarse-Grained Reconfigurable Block Encryption Array(RBEA). To improve performance and resource efficiency of the direct mapping implementation, we propose 8 modified implementations based on merger, task duplication and loop unrolling methods. Experimental results show that the improved implementations increase the throughput from 1023.99 Mbps to 13643.96 Mbps and the performance-area ratio from 63.99 Mbps/FB to 309.62 Mbps/FB, developing the superiority of array's computing resources. Compared with other platforms, our work has 1.16–13.34 times higher throughput and 3.55–11.73 times higher throughput per unit of array area.","PeriodicalId":294777,"journal":{"name":"2016 10th IEEE International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 10th IEEE International Conference on Anti-counterfeiting, Security, and Identification (ASID)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASID.2016.7873919","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, we explore different parallel mapping implementations of Advanced Encryption Standard (AES) on the Coarse-Grained Reconfigurable Block Encryption Array(RBEA). To improve performance and resource efficiency of the direct mapping implementation, we propose 8 modified implementations based on merger, task duplication and loop unrolling methods. Experimental results show that the improved implementations increase the throughput from 1023.99 Mbps to 13643.96 Mbps and the performance-area ratio from 63.99 Mbps/FB to 309.62 Mbps/FB, developing the superiority of array's computing resources. Compared with other platforms, our work has 1.16–13.34 times higher throughput and 3.55–11.73 times higher throughput per unit of array area.