A 3.3 V operation nonvolatile memory cell technology

1992 Symposium on VLSI Technology Digest of Technical Papers Pub Date : 1992-06-02 DOI:10.1109/VLSIT.1992.200636

K. Yoshikawa, E. Sakagami, S. Mori, N. Arai, K. Narita, Y. Yamaguchi, Y. Ohshima, K. Naruke

引用次数: 1

Abstract

The design and performance of a stacked-gate nonvolatile memory (EPROM/flash) cell operated with a 3.3-V/sub cc/ power supply are discussed. It is shown that optimally redesigned 5-V cells with thinner gate oxide reduced V/sub t/, and greater channel width can be operated on a 3.3-V V/sub cc/ should also be applicable to the next generation of 64-Mb devices and beyond.<>

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一种3.3 V操作非易失性存储单元技术

讨论了在3.3 v /sub / cc/电源下工作的堆叠栅非易失性存储器(EPROM/flash)电池的设计和性能。研究表明，优化设计的具有更薄栅极氧化物的5-V电池可以降低V/sub /，并且可以在3.3 V V/sub / cc/下工作，通道宽度更大，也适用于下一代64mb及以上的设备。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1992 Symposium on VLSI Technology Digest of Technical Papers

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