A 50 Gb/s TIA in 0.25µm SiGe:C BiCMOS in folded cascode architecture with pnp HBTs

I. Lopez, P. Rito, A. Awny, B. Heinemann, D. Kissinger, A. Ulusoy
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引用次数: 5

Abstract

This paper presents the design and electrical characterization of a transimpedance amplifier (TIA) implemented in a complementary 0.25 μm SiGe:C BiCMOS technology which offers a fT/fmax of 110 GHz/180 GHz for the npn and 95 GHz/140 GHz for the pnp transistor, respectively. Featuring folded cascode architecture by making use of the available pnp HBTs, the amplifier exhibits a differential transimpedance gain of 52.5 dBΩ and a 3 dB bandwidth of 32 GHz with a measured differential average input referred current noise density of 13.1 pA/√Hz, dissipating 70 mW of power. Clear eye diagrams up to 50 Gb/s data rate are reported. To the best of the authors' knowledge, this is the first time pnp transistors are used at such speed, achieving an overall performance comparable to, or better than, other TIA implementations in faster technologies.
一个50 Gb/s TIA在0.25µm SiGe:C BiCMOS折叠级联结构与pnp HBTs
本文介绍了一种采用互补0.25 μm SiGe:C BiCMOS技术实现的跨阻放大器(TIA)的设计和电气特性,该技术为npn和pnp晶体管分别提供110 GHz/180 GHz和95 GHz/140 GHz的fT/fmax。该放大器采用折叠级联结构,利用现有的pnp hbt,差分跨阻增益为52.5 dBΩ, 3db带宽为32 GHz,测量差分平均输入参考电流噪声密度为13.1 pA/√Hz,功耗为70 mW。清晰的眼图高达50 Gb/s的数据速率报告。据作者所知,这是pnp晶体管第一次以这样的速度使用,实现了与其他更快技术中的TIA实现相当或更好的整体性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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