Current sensing techniques for global interconnects in very deep submicron (VDSM) CMOS

Abstract

Sensing current instead of voltage provides an alternative to signaling on the long wires that are increasingly limiting the performance of CMOS as it scales into the VDSM regime (<0.25 /spl mu/). Current-mode techniques have been proposed for sensing bit-lines. We present a comparative study of Current-sensing with the optimal repeater insertion technique for wires from 0.35 cm to 1.75 cm in length. Simulation results using SPICE for 0.18 /spl mu/ showed that current-sensing was faster and lower-power when compared to optimal repeater insertion technique. While the power dissipated by the optimal repeater circuit increased linearly with line length, power dissipated by the current-sensing circuit was almost constant for longer lines. Inductance had little effect on the differential current sensing technique.